https://www.jianshu.com/p/e68dd8305e9c

https://blog.codedragon.tech/2017/09/25/%E6%B7%B1%E5%85%A5%E7%90%86%E8%A7%A3%E8%AE%A1%E7%AE%97%E6%9C%BA%E7%B3%BB%E7%BB%9FCacheLab-PartB%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/

https://wdxmzy.com/csapp/thick-csapp-lab-4/2016/04/16/

https://www.jianshu.com/p/582367289391

Part A:Writing a Cache Simulator

说明

• For this lab, we are interested only in data cache performance, so your simulator should ignore all
instruction cache accesses (lines starting with “I”).

• For this this lab, you should assume that memory accesses are aligned properly, such that a single
memory access never crosses block boundaries. By making this assumption, you can ignore the
request sizes in the valgrind traces.

算法

• Store
• Modify

• The data modify operation (M) is treated as a load followed by a store to the same address

• 第一轮迭代，计算最大的LRU，如果$(\text{cache[index_][i].valid_bit} == 1) \&\& (\text{cache[index_][i].tag == tag})$则hit，同时找到$\text{cache[index_][i].valid_bit} == 0$的位置
• 如果没有hit，输出miss
• 如果存在$\text{cache[index_][i].valid_bit} == 0$的位置，则直接保存结果
• 否则再次遍历，找到最大LRU对应的位置，保存结果
• 输出evict

Part B: Optimizing Matrix Transpose

$64\times 64$

https://blog.codedragon.tech/2017/09/25/%E6%B7%B1%E5%85%A5%E7%90%86%E8%A7%A3%E8%AE%A1%E7%AE%97%E6%9C%BA%E7%B3%BB%E7%BB%9FCacheLab-PartB%E5%AE%9E%E9%AA%8C%E6%8A%A5%E5%91%8A/